1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having a delay locked loop circuit.
2. Related Art
Generally, a timing skew problem arises between an external clock signal and an internal clock signal. Therefore, a circuit configured to synchronize data with a clock signal exactly is required. A delay locked loop (hereinafter, referred to as a “DLL”) circuit is widely used as a synchronization circuit. The DLL circuit is a circuit which is configured to generate a locked internal clock signal by delaying an input clock signal.
That is, a DLL circuit is configured to generate an internal clock signal a phase of which leads a phase of an input clock signal by a predetermined time, so that data may be outputted without delay relative to the input clock signal. To implement this function, a conventional DLL circuit is configured to include a clock buffer, a delay device, a phase comparison device, a delay control device, a shift register, and so on.
Such a DLL circuit operates at the same frequency as a clock frequency. Thus, as the clock frequency increases, the above-mentioned circuits operate in response to the clock signal having a high frequency, thus increasing the current consumption of the DLL circuit. Furthermore, even after the input clock signal is already locked to be suitable for the internal clock signal, the DLL circuit operates at the same frequency as the input clock signal. Consequently, unnecessary current consumption is increased.